JEDEC Approves QDRTII Family of High-Speed SRAM Products
QDRII/DDRII architectures, the industry-standard
SRAM memory for high-speed networking, offer speeds up to
333MHz, an ultra-wide data-valid window and small footprint
FPGA package
SAN JOSE, Calif., March 20, 2002 - The QDR co-development
team today announced that JEDEC has approved the complete
specifications for the team's Quad Data RateT II (QDRII) and
Double Data RateII (DDRII) SRAM product architectures. JEDEC
is the standardizing body for the solid-state electronics
section of the Electronic Industries Alliance (EIA), a trade
association that represents all areas of the electronics industry.
JEDEC has been one of the leading developer of standards for
the solid-state industry since 1958.
These QDRII/DDRII SRAM specifications set the second-generation,
high-performance communications memory standard for network
switches, routers, and other communications applications.
The approval to adopt QDR specifications as a JEDEC standard
was passed by the JEDEC board of directors at a recent association
meeting.
JEDEC's approval of the QDRII/DDRII architectures validates
customer recognition that these devices constitute an industry
standard for high-speed networking SRAM. QDRII and DDRII are
already widely used in OC192 and OC768 applications. The QDRII
specification is also being adopted as the standard for the
Network Processor (NP) Forum as the basis for Phase 1 of the
Look-Aside Interface (LA-1).
The architectures provide the specifications necessary to
enable the team's QDRII and DDRII devices to operate at speeds
up to 333 MHz, while providing an ultra-wide data valid window
of 65 percent of the clock cycle. Now designers have a complete
SRAM solution for any high-speed networking application.
The QDR co-development team unites the industry's leading
SRAM manufacturers in a collaborative effort to define proprietary
networking SRAM architectures. Current team members include
Cypress, Micron, IDT, NEC and Samsung. Hitach signed a letter
of intent to join the QDR co-development team and is currently
finalizing a formal agreement with the other QDR team members.
The new JEDEC standards extend to the package and pin rotation
specifications of QDRII and DDRII devices with densities up
to 288 Mb. The package and unique pinout standard is suitable
for all products in the QDRII/DDRII family, including QDRII
and DDRII common I/O and separate I/O devices. The 165-pin
FBGA provides customers with the flexibility to design for
future density and performance migrations while achieving
a 40 percent space savings over the traditional 209-ball,
14mm x 22mm BGA or 100-pin TQFP packages. For more information
on the specifications, please visit the QDR SRAM website at
www.qdrsram.com.
About QDR
In 1999, the QDR co-development team was created to define
a new family of SRAM architectures for high-performance communications
applications. In a revolutionary relationship, participating
companies work closely together to ensure multiple sources
for new QDR SRAMs by developing pin- and function-compatible
products. The QDR family of SRAM products incorporates extensive
input from networking industry leaders. QDR devices have two
ports running independently at twice the rate of conventional
synchronous memories, resulting in four data items per clock
cycle. The QDR family of products includes Quad Data Rate
and Double Data Rate common and separate I/O definitions.
Depending on the application, products in the QDR SRAM family
can more than double SRAM device efficiency per pin.
Quad Data RateT and QDRT SRAM comprise a new family of products
developed by Cypress, IDT, Micron Technology, Inc., NEC and
Samsung. Any other trademarks referenced herein are the property
of their respective owners.
"Safe Harbor" Statement under the Private Securities Litigation
Reform Act of 1995: Statements herein that are not historical
facts are "forward-looking statements" involving risks and uncertainties,
including by not limited to: the effect of global economic conditions,
shifts in supply and demand, market acceptance, the impact of
competitive products and pricing, product development, commercialization
and technological difficulties, and capacity and supply constraints.
Please refer to the companies' Securities and Exchange Commission
filings for discussions of such risks
QDR
and Quad Data Rate SRAMs comprise a new family of products
developed by Cypress, IDT, Micron Technology, Inc., NEC and
Samsung. All registered trademarks or trademarks are the property
of their respective owners.
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